1. Field of Invention
This invention relates to calibration of flash analog to digital converters, and more particularly relates to calibration of flash analog to digital converters utilized in data storage systems such as, for example, magnetic disk storage systems having read/write channel circuits.
2. Description of Related Art
In data storage systems data is stored on a storage media such as a CD-ROM, writable CD, DVD or other optical disk, magnetic tape, magnetic hard disk, etc. Typically, when data is read from the storage media, some form of data detection circuitry is utilized to process the signal generated from the storage media. In magnetic disk storage systems for computers, such as hard drives, digital data serves to modulate the current in a read/write head coil so that a sequence of corresponding magnetic flux transitions are written on a magnetic medium in concentric tracks. To read this recorded data, the read/write head passes over the magnetic medium and transduces the recorded magnetic transmissions into a signal of an analog nature that contains pulses that alternate in polarity. These pulses are then decoded by read/write channel circuitry to reproduce the digital data.
Decoding the pulses into a digital sequence can be performed by a simple peak detector in an analog read channel or, as in more recent designs, by using a discrete time sequence detector in a sampled amplitude read channel. Discrete time sequence detectors are preferred over simple analog pulse detectors because they compensate for intersymbol interferences (ISI) and, therefore, can recover pulses recorded at high densities. As a result, discrete time sequence detectors increase the capacity and reliability of the storage system.
There are several well known discrete time sequence detection methods for use in a sampled amplitude read/write channel circuit including discrete time pulse detection (DPD), partial response (PR) with Viterbi detection, partial response maximum likelihood (PRML) sequence detection, decision-feedback equalization (DFE), enhanced decision-feedback equalization (EDFE), and fixed-delay tree-search with decision-feedback (FDTSIDF). When discrete methods are utilized for sampled amplitude read channel systems, an analog to digital converter (ADC) is typically utilized to convert the high frequency data which is contained on disk.
One type of ADC which may be utilized to convert high frequency disk data is a flash ADC. Such an ADC may contain multiple comparators for conversion of the analog data to digital data. In order to accurately convert the high frequency analog data, it is desirable that the comparators exhibit very little electrical variation from ideal operation even in the presence of "offsets". Many sources exists for offsets including mismatch between two devices (for example transistors, resistors, capacitors, etc.) which though intended to be identical, vary to one degree or another due to limitations of fabrication processes.
One approach to compensate for such offsets is to utilize a DC auto-zero operation. FIG. 1 illustrates an example of an auto-zero operation for use with an amplifier of a flash ADC comparator. As shown in FIG. 1, a comparator having input voltages V.sub.in1 and V.sub.in2, differential transistors M.sub.1 and M.sub.2, and outputs V.sub.o1 and V.sub.2 are provided. In normal operation, switches S.sub.1 and S.sub.2 are connected to V.sub.in1 and V.sub.in2 respectively and switches S.sub.3 and S.sub.4 are open. For auto-zero operation, the switches S.sub.1 and S.sub.2 are connected to V.sub.ref1, and V.sub.ref2 respectively and switches S.sub.3 and S.sub.4 are closed. Control of the switches in this manner during auto-zero operation will bias the capacitive nodes V.sub.o1 and V.sub.o2 with the effect that the amplifier stage is biased such the output voltage (V.sub.o1 -V.sub.o2) is substantially zero with an input voltage differential of V.sub.ref1 -V.sub.ref2.
Auto-zero schemes such as described above have disadvantages in that only DC (or static) mismatches are accounted for and dynamic mismatches (from, for example, different parasitic capacitances, differential charge injection from the switches, etc.) are not corrected. Thus, during actual operation of the amplifier (as opposed to a DC auto-zero situation where the inputs are not changing) offsets will still result. Moreover the auto-zero scheme described above does not address the use of comparators having multiple amplifier stages as the DC offset of the first stage may be accounted for, but the offsets of subsequent stages are not corrected.